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FSD1000
Features
Combo Fairchild Power Switch (FPSTM)
Description
FSD1000 is a Fairchild Power Switch (FPS) that is specially designed for SMPS of personal computer. This device is a high voltage power SenseFET combined with two PWM controllers in a single monolithic device; One is for main power and the other is for auxiliary power. The PWM controllers feature integrated oscillator, under voltage lockout, optimized gate driver and temperature compensated precise current sources for the loop compensation. This device also includes various fault protection circuits such as line under/ over voltage lock out, over voltage protection, over load protection and over temperature protection. Compared with discrete MOSFET and PWM controller solution, FSD1000 can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity and system reliability * Current Mode Control for Main Power * Voltage Mode Control for Auxiliary Power * Synchronized switching of Main and Auxiliary Power (70kHz) * Internal Start-up Circuit * Internal Soft Start for Auxiliary Power * User Defined Soft Start for Main Power * Pulse by Pulse Current Limiting * Over Load Protection (Main : Latch Mode, Aux : Auto Restart Mode) * Internal Over Temperature Protection * Vcc Under Voltage Lockout * Line Under voltage/ Over Voltage Lockout * Burst Mode Operation for auxiliary power to reduce the Power Consumption in the Standby Mode * Internal High Voltage SenseFET for auxiliary power
Application
* SMPS for PC power * LCD TV Power Supply
Typical Circuit
Main Output
V STR AC IN LS2 Output
Main PWM
Isense Main Off
LS1 Aux Output
S/S
Drain
Aux PWM
GND V FB.aux ILIM
V FB.main
Vcc
Figure 1. Typical Application circuit
Rev.1.0.2
(c)2004 Fairchild Semiconductor Corporation
FSD1000
Internal Block Diagram
Drain 11 LS2 8 Vcc OVP 4.4 V 2.4 V 2.0 V H : Dmain < 0.67 L : Dmain < 0.50 21V 9.5/13.5V
Q S
Vcc 5
Vstr 12
Line OVP
Ich
Vcc good Vref Internal Bias
OSC
S Q
Gate drive GND Burst
Q
R
R
Q
Gate drive
4 Output
Q
R
OTP Vcc OVP Line OVP Main OLP Power off Reset (Vcc <6V)
Latch
S Q
PWM Comparator 6 Vcc Vcc
Idelay
ILIM 9
1:110 Vref
Idelay
0.3V
Isense
Q
S
R
Q
Vref
IFB
OSC
Auto restart
3R R
IFB
2 VFB.MAIN
VFB,AUX 1
Soft Start (10ms)
R
Aux OFF
Counter /4
Vcc good Main OLP
Vcc good Aux OLP
7V Main OFF
Vth
Vcc
ISS
Burst 0.5 V 0.7 V
4.5V 0.8 V 1.0 V 7 LS1 1.4 V 1.68 V
3 S/S Vcc good
time delay (30ms)
Figure 2. Functional Block Diagram of FSD1000
2
FSD1000
Pin Definitions
Pin Number Pin Name Pin Function Description This pin is for the feedback control of the auxiliary power. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. Voltage mode control is employed for the auxiliary power and the duty cycle ratio of Internal MOSFET for the auxiliary power is proportional to the voltage of this pin. If the voltage of this pin exceeds 4.5V, the over load protection is triggered terminating the switching operation of the main and auxiliary power (Auto-restart mode protection). This pin is for the feedback control of the main power. This pin is internally connected to the inverting input of the PWM comparator. The collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed between this pin and GND. Current mode control is employed for the main power and the peak drain current of the external MOSFET for the main power is proportional to the voltage of this pin. If the voltage of this pin exceeds 7V, the over load protection is triggered disabling the gating output for the main power (Latch mode protection). This pin is for the soft start of the main power. Soft start time is programmed by a capacitor on this pin. This pin is for the gate drive of the external MOSFET of the main power. This pin is the positive supply voltage input. During startup, the power is supplied by an internal high voltage current source that is connected to the Vstr pin. When Vcc reaches 13.5V, the internal high voltage current source is disabled and the power is supplied from auxiliary transformer winding. This pin is for the current sense of the external MOSFET for the main power. It is internally connected to the PWM comparator for the main. This pin is for line under voltage detection. When the voltage of this in drops below 1.4V the main power is shutdown. When the voltage drops below 0.8V, the auxiliary power is shutdown. This pin is for line over voltage detection and maximum duty cycle ratio change. The maximum duty cycle ratio is set to be 50% when the voltage of LS2 pin is higher than 2.4V. The maximum duty cycle ratio is increased to 67% when LS2 voltage goes below 2.0V. When the voltage of LS2 goes above 4.4V, the switching operations for the main and auxiliary powers are disabled to protect the switching devices. This pin is for the current limit of the auxiliary power. The pulse-by-pulse current limit level of the internal SenseFET is programmed by a resistor on this pin. This pin is the high voltage power SenseFET drain. It is designed to drive the auxiliary transformer directly. This pin is connected directly to the high voltage DC link. At startup, the internal high voltage current source supplies internal bias and charges the external capacitor that is connected to the Vcc pin. Once Vcc reaches 13V, the internal current source is disabled.
1
VFB,AUX
2
VFB,MAIN
3 4 5
S/S Output Vcc
6 7
ISENSE LS1
8
LS2
9 10 11
ILIM NC Drain
12
VSTR
3
FSD1000
Pin Configuration
12DIPH
VFB,AUX VFB,MAIN S/S
1 12
Vstr Drain NC
2
11
3
10
GND
GND
FSD1000
Output Vcc Isense
4
9
ILIM LS2 LS1
5
8
6
7
Figure 3. Pin Configuration (Top View)
4
FSD1000
Absolute Maximum Ratings
(Ta=25C, unless otherwise specified) Parameter Maximum Vstr Pin Voltage Continuous SenseFET Drain Current (TC=25C) Maximum Supply Voltage Input Voltage Range Operating Ambient Temperature Storage Temperature Range Symbol VSTR,MAX ID VCC,MAX VFB,MAIN / VFB,AUX TA TSTG Value 700 2 20 -0.3 to VSD -25 to +85 -55 to +150 Unit V ADC V V C C
5
FSD1000
Electrical Characteristics
(Ta=25C unless otherwise specified) Parameter SENSEFET SECTION Drain-Source Breakdown Voltage Off-State Current On-State Resistance Rising Time 2 Falling Time 2 Leading Edge
(1) (1)
Symbol BVdss Idss RDS(ON) TR2 TF2 TLEB ILIM
Condition VCC = 0V, ID = 100A VDS = 560V Tj = 25C ID = 100mA Tj = 100C ID = 100mA VDS = 350V, ID = 500mA VDS = 350V, lD = 500mA With 33 resistor between ILIM pin and ground pin Tj = 25C Ta = 25C, VFB,MAIN = 0V Ta = 25C 5V < VFB,MAIN < VSD,MAIN Ta = 25C, VFB,AUX = 0V Ta = 25C 3V < VFB,AUX < VSD,AUX VFB,AUX = 3.5V 1.4V < LS2 < 2V VFB,AUX = 3.5V 2V < LS2 < 4.4V VFB,AUX = 0V After turn on (Note 1) Vfb = 4V Ta = 25C, CL = 100pF Ta = 25C, CL = 100pF
Min. 700 0.8
Typ. 7.8 12.9 100 50 250 1.0
Max. 100 9.0 15.0 1.2
Unit V A ns ns ns A
Blanking(1)
Pulse-by-pulse current limit CONTROL SECTION Switching Frequency Main Feedback Source Current Shutdown Main Delay Current Aux. Feedback Source Current Shutdown Aux. Delay Current Maximum Duty Cycle Maximum Duty Cycle Minimum Duty Cycle UVLO Threshold Voltage SOFT START SECTION Soft Start Current Internal Soft Start Time Internal Time Delay PROTECTION SECTION Thermal Shutdown Temperature (Tj) (1) Shutdown Main Feedback Voltage Shutdown Aux. Feedback Voltage OUTPUT SECTION Rising Time 1 (1) Falling Time 1 (1)
Fosc IFB,MAIN IDELAY,MAIN IFB,MAIN IDELAY,MAIN Dmax Dmax Dmin Vstart Vstop ISOFT TSS Td TSD VSD,MAIN VSD,AUX TR1 TF1
61 0.6 3.5 0.3 3.5 62 45 12.5 8.5 35 140 6.0 4.0 -
67 0.7 5.0 0.4 5.0 67 50 0 13.5 9.5 45 10 30 160 7.0 4.5 45 35
73 0.8 6.5 0.5 6.5 72 55 0 14.5 10.5 55 8.0 5.0 150 150
kHz mA uA mA uA % % % V V uA ms ms C V V ns ns
Note: 1. These parameters, although guaranteed, are not 100% tested in production
6
FSD1000
Electrical Characteristics (Continued)
(Ta=25C unless otherwise specified) Parameter LINE SENSE SECTION Line Over Voltage PWM Max Duty Control Voltage Hysteresis Main Off Voltage Hysteresis Aux. Off Voltage Hysteresis BURST MODE SECTION Burst Mode Voltage Hysteresis TOTAL DEVICE SECTION Start up Chragng Current Operating Supply Current Ich Iop VCC = 0V, VSTR = min. 30V Ta = 25C, VCC = 18V 1.5 4 2.3 5 mA mA BURST 0.7 200 V mV Aux OFF Main OFF BUS OVP Max Duty 4.0 2.0 1.17 0.67 4.4 2.4 400 1.4 280 0.8 200 5.0 2.8 1.63 0.93 V V mV V mV V mV Symbol Condition Min. Typ. Max. Unit
7
FSD1000
Typical Performance Characteristics
(Some characteristic Graphs are Normalized at Ta= 25C)
1.3
1.3
1.2
1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8
0.8
0.7 -40
-20
0
20
40
60
80
100
120
140
0.7 -40
-20
0
20
40
60
80
100
120
140
Iop
Ifb_aux
Figure 1. Normalized Operating Current vs. Temp
1.3
Figure 2. Normalized Aux feedback current vs. Temp
1.3
1.2
1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8
0.8
0.7 -40
-20
0
20
40
60
80
100
120
140
0.7 -40
-20
0
20
40
60
80
100
120
140
Ifb
Fosc
Figure 3. Normalized Main feedback current vs. Temp
Figure 4. Normalized Operating Freqency vs. Temp
700 650 600
550
500
450
550
400
500
350
450
300
400 350 300 -40
250
200 -40
-20
0
20
40
60
80
100
120
140
-20
0
20
40
60
80
100
120
140
Isouce
Isink
Figure 5. Output source current (mA) vs. Temp
Figure 6. Output sink Current (mA) vs. Temp
8
FSD1000
Functional Description
1. Startup : At startup, an internal high voltage current source supplies the internal bias and charges the external capacitor that is connected to the Vcc pin as illustrated in figure 4. When Vcc reaches 13.5 V, the FPS begins switching operation and the internal high voltage current source is disabled. Then, the FPS continues its normal switching operation unless Vcc goes below the stop voltage of 9.5 V and the power is supplied from the auxiliary transformer winding. Once the auxiliary power starts up, the main power starts up with a time delay of 30ms.
DC link voltage
ILIM pin. Since the sense ratio is 1/110 and the reference voltage of the comparator is 0.3V, the pulse-by-pulse current limit level (ICL) is given by
I CL = 110 x 0.3 ----------------------R LIM
(A)
LS2 5 Max duty control
2.0 V 2.4 V
OSC
S Q
R
Q
Gate drive
4 Output
Vcc 3 6
Vstr
6 Isense Vcc Vcc
Idelay
Istart
Vref Vcc good 9.5V/13.5V Internal Bias
PWM Comparator R
3R
IFB
VFB.MAIN 2
D2
D1
CFB
Figure 5. PWM control block for the main power
Figure 4. Internal startup circuit
Drain 11
2. Feedback Control : FSD1000 has two PWM controllers in a single package; one is for the main power and the other is for the auxiliary power. The PWM block for the main controls the external MOSFET, while the PWM block for the auxiliary power controls the internal SenseFET. 2.1 Feedback Control for the main power : Figure 5 illustrates the simplified PWM block for the main power. The current mode control is employed for the main power. The voltage of the feedback pin is compared with the current sense voltage for pulse width modulation (PWM). As shown in figure 5, the feedback voltage determines the peak value of the drain current of the external power MOSFET for main power. Usually opto-coupler is used to implement feedback network. The collector of the opto-coupler transistor is connected to feedback pin and the emitter is connected to the ground pin. For stable operation, a capacitor should be placed between this pin and GND. 2.2 Feedback Control for the auxiliary power : Figure 6 shows the internal high voltage SenseFET together with PWM block for auxiliary power. Auxiliary power employs voltage mode control and the feedback pin voltage is compared with internal ramp signal for pulse width modulation (PWM). The pulse-by-pulse current limit level of the SenseFET is programmed by an external resistor on the 9
Q
S
OSC
Gate drive GND 1/110 Burst
Q
R
ILIM 9 R LIM Vref V FB,AUX 4 D1 C FB D2 R
Soft start I delay
0.3V Vref OSC
I FB
Figure 6. PWM control block for the auxiliary power
3. Protection Circuit : Besides pulse-by-pulse current limit, FSD1000 has various self protection functions; over load protections (OLP) for main and auxiliary powers, over voltage protection (OVP), line over/under voltage lockout and over temperature protection (OTP). Because these protection circuits are fully integrated into the IC without external components, the reliability can be improved. In the event of fault conditions such as OLP of auxiliary power and
FSD1000
line under voltage lockout, FSD1000 enters into auto restart operation. Once the fault condition occurs, switching is terminated and the SenseFET remains off. This causes Vcc to fall. When Vcc reaches the stop voltage (9.5V), the internal startup circuit charges Vcc capacitor up to start voltage (13.5V). When Vcc reaches 13.5V, the internal startup circuit is disabled and Vcc is discharged down to 9.5V. In this manner, FSD1000 repeats charging and discharging Vcc capacitor 4 times. After then, the protection is reset and the FSD1000 resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power SenseFET until the fault condition is eliminated as shown Figure 7. Meanwhile, FSD1000 enters into latch mode in the case of Vcc OVP, Line OVP and Main OLP and OTP. The fault latch is reset only when Vcc is fully discharged below 6V by un-plugging the AC line as shown in Figure 8.
3.1 Over Load Protection : Over load means that the load current exceeds a pre-set level due to an abnormal situation. In this situation, protection circuit should be triggered in order to protect the SMPS. Because of the pulse-by-pulse current limit capability, the maximum peak current through the SMPS is limited, and therefore the maximum input power is restricted with a given input voltage. If the output consumes beyond this maximum power, the output voltage (Vo) decreases below the set voltage. This reduces optocoupler transistor current increasing feedback voltage (Vfb). If the inverting input of PWM comparator reaches its maximum value, D1 is blocked and the current source Idelay starts to charge CFB slowly compared to when the current source IFB charges CFB. In this condition, the feedback voltage continues increasing until it reaches OLP threshold, and the switching operation is terminated at that time. The OLP for the auxiliary power is auto restart mode while OLP for the main is latch mode. 3.2 Line Under voltage lockout : The switching operation for the main power is terminated when the voltage of LS1 drops below 1.4V and the switching operation for auxiliary power is terminated when this voltage goes below 0.8V. 3.3 Over voltage protection : In an abnormal situation such as feedback loop open, the supply voltage for FSD1000 (Vcc) may rise above the breakdown voltage of the FPS. In order to protects the FPS from the over voltage damage, FSD1000 employs over voltage protection for Vcc. If Vcc exceeds 21V, OVP circuit is triggered resulting in a termination of switching operation of both main and auxiliary powers. In order to avoid undesired triggering of OVP during normal operation, Vcc should be properly designed to be below 21V. 3.4 Line Over voltage protection : When the voltage of LS2 rises above below 4.4V, the switching operations for the main and auxiliary powers are disabled to protect the switching devices.
Over Load of Aux
Over Load removed
13.5V 9.5V
Vcc
Aux Vds
Restart
Figure 7. Auto restart mode protection
Latch Reset OTP, Vcc OVP, Line OVP, Main OLP AC power Off AC power On
13.5V 9.5V 6V
3.5 Over Temperature Protection : The thermal shutdown circuitry senses the junction temperature. The threshold is set at 160C. When the junction temperature rises above this threshold, the switching operations of main and auxiliary powers are disabled. 4. Burst Mode Operation : In order to minimize the power dissipation in the standby mode, FDS1000 has burst operation for the auxiliary power. The FPS enters into the burst mode when the feedback voltage decreases as the load decreases. The operation principle of the burst mode is illustrated in Figure 9. When the feedback voltage drops below 0.5V, the FPS stops the switching operation. Then, the output voltage decreases below the set voltage, which increases the feedback voltage. When the feedback voltage rises above 0.7V, the FPS resumes the switching operation and the feedback voltage decreases. When the feedback voltage drops below 0.5V again, the FPS ceases the
Vcc
Aux Vds
Figure 8. Latch mode protection
10
FSD1000
switching operation. In this manner, the burst operation alternately enables and disables the switching of the power MOSFET to reduce the switching loss in the standby mode.
Vo
Vo set
M ain O utput
VFB
0.70V 0.50V
M ain O ff
Ids
A ux O u tp ut
Vds
time
Figure 9. Waveforms of burst operation
5. Sequence of start-up and shutdown : FSD1000 has a sequence of the startup and shutdown operation between main and auxiliary powers. As can be seen in Figure 11, main power starts up with 30 ms time delay after auxiliary power starts up. When the AC line is powered off, the main power shuts down first as the voltage of LS1 pin drops below 1.4V. The auxiliary power shuts down when the voltage of LS1 drops below 0.8V. Figure 12 shows the shutdown and restart sequence in the case of auto restart mode protection. When the protection is triggered, main and auxiliary powers shut down together. When FSD1000 restarts, the auxiliary power starts up first and the main power starts up after 30ms. Figure 13 shows the shutdown and restart sequence in the case of latch mode protection. When the protection is triggered, main and auxiliary powers shut down together and Vcc continues being charged and discharged until Vcc is fully discharged. The protection is reset when Vcc is discharged below 6V by unplugging the AC line. Figure 14 shows the remote ON/OFF of the main power. The remote ON/OFF of the main power is easily implemented using a transistor connected to the cathode of KA431 in the main power feedback network as shown in Figure 10. When the transistor is turned on, the current through the opto-coupler increases pulling down the feedback voltage to almost zero. The main starts up with soft-start when the transistor is turned off.
Figure 10. Remote ON/OFF of Main power
11
FSD1000
AC power on
AC power off
AC power on
AC Line voltage
LS1<1.4V LS1<0.8V
DC link voltage
13.5V 9.5V
Vcc
Aux drain current Tss=10ms Tss=10ms
Main drain current Td=30ms Td=30ms
Figure 11. Typical Waveforms (1)
OLP of Aux
Auto Restart
13.5V 9.5V
Vcc
Aux drain current Tss=10ms Tss=10ms
Main drain current Td=30ms Td=30ms
Figure 12. Typical Waveforms (2)
12
FSD1000
Vcc OVP, Line OVP, Main OLP or OTP
AC Power off Latch reset AC Power ON
13.5V 9.5V 6V
Vcc
Aux drain current Tss=10ms Tss=10ms
Main drain current Td=30ms Td=30ms
Figure 13. Typical Waveforms (3)
Main Off by pulling down VFB
Main ON
Main VFB
13.5V
Vcc
Aux drain current Tss=10ms
Main drain current Td=30ms
Figure 14. Typical Waveforms (4)
13
Main power : 5V (12A), 3.3V (12A) Aux. power : 5V (2A)
Output voltage (Max current)
10 R201 VDC 1 1 2 T 1 EI3329 14 1 21 1
472 C201 2
L201 EER2834
1
2
1
12
5V D201 R104 33K/3W 1 C108 2 222,1kV 13 MBRF3060PT
3
F1
2
t
2
2
1 FUSE RT 1 10D9 2 JP2 1 2 3 2 2 C101 473/275VAC 1 2 C102 473/275VAC 1 2 HEADER 3 C103 222/3kV C105 222/3kV 1 3
21
2
4-
+2
2
2
LF1
3 1
12 10 R203 D101 UF4007 1 4 11 1 5 1 R102 500K 1 C106 470uF,200V 10 21 1 472 C203 2
4
9
5
8
GND_S
6
7
1
2
2
Line f ilter
BD1 GSIB660 C107 470uF,200V 1
21
C202 472
2
11
1 R101 500K
R202 10
1
3
10
C205 2200uF,10V
GND_S
3.3V Q1 FQA10N80 6 2 9 D202 MBRF3060PT 2 3 D 7 8
21
C204 472
1 2
1
Low standby mode power consumption (<1W at 240Vac input and 0.5W load) Low component count Enhanced system reliability through various protection functions Internal soft-start (10ms)
1
2 1 R105 1K Is R103 10K 2 C109 102 Is 1N4745 D103 G ND_P 2 2 1 1 2 3
S
2
0
LS
Gate
1G
GND_S R106 0.1/2W 1
with voltage doubler
Universal input
Input voltage
T2 EE1625 1 GND_P GND_P R109 30k D102 2 1 1 2 2 10
2
0
C104 222/3kV
R204 10
1
C206 2200uF,10V
GND_S
2 1 2 1 UF4004 9
R216 10k
C 110
47uF,50V 2 U1 7 LS1 Isense 6
R107 10/0.5W 3 GP30G 1 Drain 4 2 GND_P D203 L202 2uH
R205 1k
2
LS
2
5V_aux
R208 3.2k
VFB1 C115 473 R112 33 1 1 2 8 9 LS2 I_LIM 14 Vcc Output 5 D104 1 5 GND GND_P 10 Drain VDC 11 12 GND 13 1 R110 30 NC Drain Vstart FSD1000 S/S VFB.main VFB.aux 3 2 GND_P VFB1 2 1 VFB2 2 2 C113 1uF C111 103 C112 473 1 1 1 GND_S 2 1N4745 D105 2 R111 10k 1 VFB2 11 4 1 R213 1k UF4003 2 1 R108 50K/3W VDC 2 2 C114 222,1kV 6 1 7 1 4 2 1 Gate 2 UF4007 C207 470uF,16V 2 2 C208 470uF,16V D106 18 2 1 2
4
P1 817A
1
2
C210 100nF
R207 33k
1
Output power
2
1
2
1
3
Typical application circuit
GND_P
3
2
1
110W
IC1 T L431
2
R209 5k 2 2
3
S1 R212 1k C209 47nF 1 GND_P GND_P P2 817A 3 2 2 1 2 R211 33k 1 1 R214 10k
2
SW SPDT
1
2
GND_S
R210
4.7k 3
2
1 2 GND_P 2 IC2 T L431
2
1
Q2 2N2222 R215 10k
PC power supply
Application
1
GND_S
1. Schematic
Features
FSD1000
3
GND_S
1
1
R206 1k
1
1
14 * * * *
FSD1000
2.1 Main Transformer Schematic Diagram
1 NP/2 2 3 NP/2 4 5 6 7
14 3 13 +5V 12 11 10 9 8 Bobbin +3.3V BOTTOM NP/2 N5V N3.3V NP/2 TOP 3
* THE '
' MARKS ARE START POINT.
CORE : EI3329 BOBBIN : EI3329
2.2 Main Transformer Winding Specification
No NP/2 N3.3V N5V NP/2
Pin (sf) 13 10 8 14 12 35
Wire 0.5 x 1 0.4 x 6 0.4 x 6 0.5 x 1
Turns 24 2 3 24
Winding Method Solenoid Winding Center Winding Center Winding Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers Insulation: Polyester Tape t = 0.050mm, 2Layers Insulation: Polyester Tape t = 0.050mm, 2Layers Outer Insulation: Polyester Tape t = 0.050mm, 2Layers
2.3 Main Transformer Electrical Characteristics
Pin Inductance Leakage Inductance 1-5 1-5
Specification 9mH 10% 10uH Max
Remarks 100kHz, 1V 2nd all short
15
FSD1000
3.1 Main inductor Schematic Diagram
3 6 5 4 3 2 1
3
N3.3V
N5V
N5V
TOP
N3.3V 7 8 9 10 11 12 Bobbin * THE ' ' MARKS ARE START POINT.
CORE : EER2834 BOBBIN : EER2834
3.2 Main inductor Winding Specification
No N5V N3.3V
Pin (sf) 1 12 67
Wire 0.4 x 8 0.4 x 8
Turns 9 6
Winding Method Center Winding Solenoid Winding
Insulation: Polyester Tape t = 0.050mm, 2Layers Insulation: Polyester Tape t = 0.050mm, 2Layers
3.3 Main inductor Electrical Characteristics
Pin Inductance 1 - 12
Specification 15 uH 10%
Remarks 100kHz, 1V
16
FSD1000
4.1 Auxiliary Transformer Schematic Diagram
10 3 2 3 4 NP/2 5 NP/2 6 7 Bobbin * THE ' ' MARKS ARE START POINT. 8 +5V 9 BOTTOM NP/2 NVcc N5V NP/2 TOP 3
1 NVcc
CORE : EE1625 BOBBIN : EE1625
4.2 Auxiliary Transformer Winding Specification
No NP/2 N5V NVcc NP/2
Pin (sf) 45 87 21 56
Wire 0.15 0.2
Turns 75 9 25 75
Winding Method Solenoid Winding Solenoid Winding Solenoid Winding Solenoid Winding
0.5

0.15
4.3 Auxiliary Transformer Electrical Characteristics
Pin Inductance Leakage Inductance 4-6 4-6
Specification 1.35mH 10% 60uH Max
Remarks 100kHz, 1V 2nd all short
17
FSD1000
5. Layout Auxiliary Transformer Electrical Characteristics
18
FSD1000
Package Dimensions
12DIPH-300
19
FSD1000
Ordering Information
Product Number FSD1000 Package 12-DIPH Package Marking FSD1000 Rdson max 9
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 7/9/04 0.0m 001 2004 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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